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| a FEATURES DC PERFORMANCE 1 mV max Input Offset Voltage Low Offset Drift: 20 V/ C 1 pA max Input Bias Current Input Bias Current Guaranteed Over Full Common-Mode Voltage Range AC PERFORMANCE 3 V/ s Slew Rate 1 MHz Unity Gain Bandwidth Low Input Voltage Noise: 4 V p-p, 0.1 Hz to 10 Hz Available in a Low Cost, 8-Pin Plastic Mini-DIP Standard Op Amp Pinout APPLICATIONS Electrometer Amplifiers Photodiode Preamps pH Electrode Buffers Log Ratio Amplifiers 1 pA Monolithic Electrometer Operational Amplifier AD546* CONNECTION DIAGRAM 8-Pin Plastic Mini-DIP Package PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS The AD546 is a monolithic electrometer combining the virtues of low (1 pA) input bias current with the cost effectiveness of a plastic mini-DIP package. Both input offset voltage and input offset voltage drift are laser trimmed, providing very high performance for such a low cost amplifier. Input bias currents are reduced significantly by using "topgate" JFET technology. The 1015 common-mode impedance, resulting from a bootstrapped input stage, insures that input bias current is essentially independent of common-mode voltage variations. The AD546 is suitable for applications requiring both minimal levels of input bias current and low input offset voltage. Applications for the AD546 include use as a buffer amplifier for current output transducers such as photodiodes and pH probes. It may also be used as a precision integrator or as a low droop rate sample and hold amplifier. The AD546 is pin compatible with standard op amps; its plastic mini-DIP package is ideal for use with automatic insertion equipment. The AD546 is available in two performance grades, all rated over the 0C to +70C commercial temperature range, and packaged in an 8-pin plastic mini-DIP. *Covered by Patent No. 4,639,683. 1. The input bias current of the AD546 is specified, 100% tested and guaranteed with the device in the fully warmed-up condition. 2. The input offset voltage of the AD546 is laser trimmed to less than 1 mV (AD546K). 3. The AD546 is packaged in a standard, low cost, 8-pin mini-DIP. 4. A low quiescent supply current of 700 A minimizes any thermal effects which might degrade input bias current and input offset voltage specifications. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD546-SPECIFICATIONS (@ +25 C and Model INPUT BIAS CURRENT1 Either Input Either Input Either Input @ TMAX Either Input Offset Current Offset Current @ TMAX INPUT OFFSET Initial Offset Offset @ TMAX vs. Temperature vs. Supply vs. Supply Long-Term Stability INPUT VOLTAGE NOISE Conditions VCM = 0 V VCM = 10 V VCM = 0 V VCM = 10 V VCM = 0 V VCM = 0 V 15 V dc, unless otherwise noted) Min AD546J Typ 0.2 0.1 40 40 0.17 13 2 3 20 20 100 100 20 20 4 90 60 35 35 1.3 0.4 1013 1 1015 0.8 300 300 100 80 1000 800 250 200 20 +10 90 80 +12 +10 35 -10 84 76 -12 -10 15 +10 100 80 +12 +10 35 4 90 60 35 35 1.3 0.4 1013 1 1015 0.8 300 300 100 80 1000 800 250 200 20 100 100 Max 1 1 Min AD546K Typ 0.2 0.2 20 20 0.09 7 1 2 Max 0.5 0.5 Units pA pA pA pA pA pA pA mV V/C V/V V/V V/Month V p-p nV/Hz nV/Hz nV/Hz nV/Hz fA rms fA/Hz pF pF V/mV V/mV V/mV V/mV V V dB dB V V mA pF TMIN-TMAX f = 0.1 Hz to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz f = 0.1 Hz to 10 Hz f = 1 kHz VDIFF = 1 V VCM = 10 V VO = 10 V RLOAD = 10 k VO = 10 V RLOAD = 10 k VO = 10 V RLOAD = 2 k VO = 10 V RLOAD = 2 k INPUT CURRENT NOISE INPUT IMPEDANCE Differential Common Mode OPEN LOOP GAIN TMIN-TMAX TMIN-TMAX INPUT VOLTAGE RANGE Differential3 Common-Mode Voltage Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Voltage Current Load Capacitance Stability VCM = 10 V TMIN to TMAX RLOAD = 10 k RLOAD = 2 k Short Circuit Gain = +1 -10 80 76 -12 -10 15 20 4000 20 4000 -2- REV. A AD546 Model FREQUENCY RESPONSE Gain BW, Small Signal Full Power Response Slew Rate, Unity Gain Settling Time Overload Recovery POWER SUPPLY Rated Performance Operating Range Quiescent Current Transistor Count PACKAGE OPTIONS Plastic Mini-DIP (N-8) Conditions G = -1 VO = 20 V p-p G = -1 to 0.1% to 0.01% 50% Overdrive Gain = -1 Min 0.7 2 AD546J Typ 1.0 50 3 4.5 5 2 15 5 # of Transistors 0.60 50 AD546JN 18 0.7 5 0.60 50 AD546KN Max Min 0.7 2 AD546K Typ 1.0 50 3 4.5 5 2 15 18 0.7 Max Units MHz kHz V/s s s s V V mA NOTES 1 Bias current specifications are guaranteed maximum, at either input, after 5 minutes of operation at T A = +25C. Bias current increases by a factor of 2.3 for every 10C rise in temperature. 2 Input offset voltage specifications are guaranteed after 5 minutes of operation at T A = +25C. 3 Defined as max continuous voltage between inputs, such that neither exceeds 10 V from ground. Specifications subject to change without notice. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. ABSOLUTE MAXIMUM RATINGS 1 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 500 mW Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and -VS Storage Temperature Range . . . . . . . . . . . . . -65C to +125C Operating Temperature Range . . . . . . . . . . . . . . 0C to +70C Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300C NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 For supply voltages less than 18 V, the absolute maximum input voltage is equal to the supply voltage. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD546 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. A -3- AD546-Typical Characteristics (V = S 20 OUTPUT VOLTAGE RANGE V 15 V, unless otherwise noted) 30 OUTPUT VOLTAGE SWING - Volts p-p 20 +25oC RL = 10k 25 INPUT VOLTAGE RANGE V 15 +VIN 10 -VIN 5 15 +VOUT 20 10 -VOUT 15 VS = 15 VOLTS 10 5 5 0 0 0 0 10 15 5 SUPPLY VOLTAGE V 20 0 10 15 5 SUPPLY VOLTAGE V 20 10 100 1k 10k LOAD RESISTANCE - 100k Figure 1. Input Voltage Range vs. Supply Voltage Figure 2. Output Voltage Range vs. Supply Voltage Figure 3. Output Voltage Swing vs. Resistive Load COMMON MODE REJECTION RATIO - dB 800 120 3000 QUIESCENT CURRENT - A 700 OPEN LOOP GAIN - V/mV 110 1000 100 600 90 300 RL = 10k 500 80 400 0 5 10 15 SUPPLY VOLTAGE V 20 70 -15 100 +15 -10 0 +10 INPUT COMMON MODE VOLTAGE - V 0 5 10 15 SUPPLY VOLTAGE V 20 Figure 4. Quiescent Current vs. Supply Voltage Figure 5. CMRR vs. Input Common-Mode Voltage Figure 6. Open Loop Gain vs. Supply Voltage 3000 30 300 OPEN LOOP GAIN - V/mV 25 INPUT BIAS CURRENT - fA 250 1000 |VOS| -V 20 15 200 300 RL = 10k 10 150 +25oC 100 -10 5 100 -55 -25 5 35 65 TEMPERATURE - oC 95 125 0 0 1 2 3 4 5 6 WARM-UP TIME - Minutes 7 -5 0 5 COMMON-MODE VOLTAGE - Volts 10 Figure 7. Open Loop Gain vs. Temperature Figure 8. Change in Offset Voltage vs. Warm-Up Time Figure 9. Input Bias Current vs. Common-Mode Voltage -4- REV. A AD546 300 160 100k WHENEVER JOHNSON NOISE IS GREATER THAN AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE CONSIDERED NEGLIGIBLE FOR THE APPLICATION. NOISE SPECTRAL DENSITY - nV/Hz 140 INPUT NOISE VOLTAGE - V p-p 120 100 80 60 40 20 INPUT BIAS CURRENT - fA 10k 1 kHz BANDWIDTH 250 1k RESISTOR JOHNSON NOISE 200 100 10 Hz BANDWIDTH 10 150 +25oC 100 1 AMPLIFIER GENERATED NOISE 0 5 10 15 SUPPLY VOLTAGE VOLTS 20 10 100 1k 10k 0.1 100k FREQUENCY - Hz 1M 10M 100M 1G 10G SOURCE RESISTANCE - Ohms 100G Figure 10. Input Bias Current vs. Supply Voltage Figure 11. Input Voltage Noise Spectral Density vs. Frequency Figure 12. Noise vs. Source Resistance 100 80 100 OUTPUT VOLTAGE SWING - V 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k 1M 80 60 40 20 0 -20 -40 10M 60 40 20 0 -20 -40 10 100 1k 10k 100k FREQUENCY - Hz 1M PHASE MARGIN - Degrees OPEN LOOP GAIN - dB FREQUENCY - Hz Figure 13. Open Loop Frequency Response Figure 14. Large Signal Frequency Response Figure 15. CMRR vs. Frequency Figure 16. PSRR vs. Frequency Figure 17. Output Settling Time vs. Output Swing and Error Voltage REV. A -5- AD546 Figure 18. Unity Gain Follower Figure 19. Unity Gain Follower Large Signal Pulse Response Figure 20. Unity Gain Follower Small Signal Pulse Response Figure 21. Unity Gain Inverter Figure 22. Unity Gain Inverter Large Signal Pulse Response Figure 23. Unity Gain Inverter Small Signal Pulse Response MINIMIZING INPUT CURRENT The AD546 is guaranteed to have less than 1 pA max input bias current at room temperature. Careful attention to how the amplifier is used will reduce input currents in actual applications. The amplifier operating temperature should be kept as low as possible to minimize input current. Like other JFET input amplifiers, the AD546's input current is sensitive to chip temperature, rising by a factor of 2.3 for every 10C rise. This is illustrated in Figure 24, a plot of AD546 input current versus ambient temperature. On-chip power dissipation will raise chip operating temperature causing an increase in input bias current. Due to the AD546's low quiescent supply current, chip temperature when the (unloaded) amplifier is operated with 15 V supplies, is less than 3C higher than ambient. The difference in input current is negligible. However, heavy output loads can cause a significant increase in chip temperature and a corresponding increase in input current. Maintaining a minimum load resistance of 10 k is recommended. Input current versus additional power dissipation due to output drive current is plotted in Figure 25. Figure 24. AD546 Input Bias Current vs Ambient Temperature Figure 25. AD546 Input Bias Current vs. Additional Power Dissipation -6- REV. A AD546 Circuit Board Notes The AD546 is designed for through hole mount into PC boards. Maintaining picoampere level resolution in that environment requires a lot of care. Since both the printed circuit board and the amplifier's package have a finite resistance, the voltage difference between the amplifier's input pin and other pins (or traces on the PC board) will cause parasitic currents to flow into (or out of) the signal path (see Figure 26). These currents can easily exceed the 1 pA input current level of the AD546 unless special precautions are taken. Two successful methods for minimizing leakage are guarding the AD546's input lines and maintaining adequate insulation resistance. The AD546's positive input (Pin 3) is located next to the negative supply voltage pin (Pin 4). The negative input (Pin 2) is next to the balance adjust pin (Pin 1) which is biased at a potential close to the negative supply voltage. The layouts shown in Figures 27a and 27b for the inverter and follower connections will guard against the effects of low surface resistance of the board. Note that the guard traces should be placed on both sides of the board. In addition the input trace should be guarded on both of its edges along its entire length. Figure 26. Sources of Parasitic Leakage Currents Figure 27a. Guarding Scheme--Inverter Figure 27b. Guarding Scheme--Follower REV. A -7- AD546 Figure 28. Input Pin to Insulating Standoff Leakage through the bulk of the circuit board will still occur with the guarding schemes shown in Figures 27a and 27b. Standard "G10" type printed circuit board material may not have high enough volume resistivity to hold leakages at the subpicoampere level particularly under high humidity conditions. One option that eliminates all effects of board resistance is shown in Figure 28. The AD546's sensitive input pin (either Pin 2 when connected as an inverter, or Pin 3 when connected as a follower) is bent up and soldered directly to a Teflon* insulated standoff. Both the signal input and feedback component leads must also be insulated from the circuit board by Teflon standoffs or low-leakage shielded cable. Contaminants such as solder flux on the board's surface and on the amplifier's package can greatly reduce the insulation resistance between the input pin and those traces with supply or signal voltages. Both the package and the board must be kept clean and dry. An effective cleaning procedure is to first swab the surface with high grade isopropyl alcohol, then rinse it with deionized water and, finally, bake it at 80C for 1 hour. Note that if either polystyrene or polypropylene capacitors are used on the printed circuit board, a baking temperature of 70C is safer, since both of these plastic compounds begin to melt at approximately +85C. Other guidelines include making the circuit layout as compact as possible and reducing the length of input lines. Keeping circuit board components rigid and minimizing vibration will reduce triboelectric and piezoelectric effects. All precision high impedance circuitry requires shielding from electrical noise and interference. For example, a ground plane should be used under all high value (i.e., greater than 1 M) feedback resistors. In some cases, a shield placed over the resistors, or even the entire amplifier, may be needed to minimize electrical interference originating from other circuits. Referring to the equation in Figure 26, this coupling can take place in either, or both, of two different forms--coupling via time varying fields: dV C dT P Table I. Insulating Materials and Characteristics Volume Resistivity ( -CM) 1017-1018 1017-1018 1016-1018 1014-1018 1012-1018 1012-1014 1010-1017 1010-1015 105-1012 Minimal Triboelectric Effects W W M M W W W G W Minimal Resistance Piezoelectric to Water Effects Absorption W M G G M M M M G G G G M M W W G W Material1 Teflon* Kel-F** Sapphire Polyethylene Polystyrene Ceramic Glass Epoxy PVC Phenolic G-Good with Regard to Property. M-Moderate with Regard to Property. W-Weak with Regard to Property. Electronic Measurements, pp.15-17, Keithley Instruments, Inc., Cleveland, Ohio, 1977. *Teflon is a registered trademark of E.I. du Pont Co. **Kel-F is a registered trademark of 3M Company. 1 OFFSET NULLING The AD546's input offset voltage can be nulled by using balance Pins 1 and 5, as shown in Figure 29. Nulling the input offset voltage in this fashion will introduce an added input offset voltage drift component of 2.4 V/C per millivolt of nulled offset. or by injection of parasitic currents by changes in capacitance due to mechanical vibration: dCp V dT Both proper shielding and rigid mechanical mounting of components help minimize error currents from both of these sources. Table I lists various insulators and their properties. Figure 29. Standard Offset Null Circuit The circuit in Figure 30 can be used when the amplifier is used as an inverter. This method introduces a small voltage in series with the amplifier's positive input terminal. The amplifier's -8- REV. A AD546 input offset voltage drift with temperature is not affected. However, variation of the power supply voltages will cause offset shifts. Figure 32. Inverter Pulse Response with 1 M Source and Feedback Resistance Figure 30. Alternate Offset Null Circuit for Inverter AC RESPONSE WITH HIGH VALUE SOURCE AND FEEDBACK RESISTANCE Source and feedback resistances greater than 100 k will magnify the effect of input capacitances (stray and inherent to the AD546) on the ac behavior of the circuit. The effects of common-mode and differential-input capacitances should be taken into account since the circuit's bandwidth and stability can be adversely affected. In a follower, the source resistance, RS, and input commonmode capacitance, CS (including capacitance due to board and capacitance inherent to the AD546), form a pole that limits circuit bandwidth to 1/2 RSCS. Figure 31 shows the follower pulse response from a 1 M source resistance with the amplifier's input pin isolated from the board, only the effect of the AD546's input common-mode capacitance is seen. Figure 33. Inverter Pulse Response with 1 M Source and Feedback Resistance, 1 pF Feedback Capacitance COMMON-MODE INPUT VOLTAGE OVERLOAD The rated common-mode input voltage range of the AD546 is from 3 V less than the positive supply voltage to 5 V greater than the negative supply voltage. Exceeding this range will degrade the amplifier's CMRR. Driving the common-mode voltage above the positive supply will cause the amplifier's output to saturate at the upper limit of output voltage. Recovery time is typically 2 s after the input has been returned to within the normal operating range. Driving the input common mode voltage within 1 V of the negative supply causes phase reversal of the output signal. In this case, normal operation is typically resumed within 0.5 ms of the input voltage returning within range. DIFFERENTIAL INPUT VOLTAGE OVERLOAD A plot of the AD546's input current versus differential input voltage (defined as VIN+ -VIN-) appears in Figure 34. The Figure 31. Follower Pulse Response from 1 M Source Resistance In an inverting configuration, the differential input capacitance forms a pole in the circuit's loop transmission. This can create peaking in the ac response and possible instability. A feedback capacitance can be used to stabilize the circuit. The inverter pulse response with RF and RS equal to 1 M, and the input pin isolated from the board appears in Figure 32. Figure 33 shows the response of the same circuit with a 1 pF feedback capacitance. Typical differential input capacitance for the AD546 is 1 pF. Figure 34. Input Current vs. Differential Input Voltage REV. A -9- AD546 input current at either terminal stays below a few hundred femtoamps until one input terminal is forced higher than 1 V to 1.5 V above the other terminal. Under these conditions, the input current limits at 30 A. INPUT PROTECTION than 1 pA), such as the FD333's should be used, and should be shielded from light to keep photocurrents from being generated. Even with these precautions, the diodes will measurably increase the input current and capacitance. In order to achieve the low input bias currents of the AD546, it is not possible to use the same on-chip protection as used in other Analog Devices op amps. This makes the AD546 sensitive to handling and precautions should be taken to minimize ESD exposure whenever possible. The AD546 safely handles any input voltage within the supply voltage range. Subjecting the input terminals to voltages beyond the power supply can destroy the device or cause shifts in input current or offset voltage if the amplifier is not protected. A protection scheme for the amplifier as an inverter is shown in Figure 35. The protection resistor, RP, is chosen to limit the current through the inverting input to 1 mA for expected transient (less than 1 second) overvoltage conditions, or to 100 A for a continuous overload. Since RP is inside the feedback loop, and is much lower in value than the amplifier's input resistance, it does not affect the inverter's dc gain. However, the Johnson noise of the resistor will add root sum of squares to the amplifier's input noise. Figure 35. Inverter with Input Current Limit In the corresponding version of this scheme for a follower, shown in Figure 36, RP and the capacitance at the positive input terminal will produce a pole in the signal frequency response at a f = 1/2 RC. Again, the Johnson noise of RP will add to the amplifier's input voltage noise. Figure 37 is a schematic of the AD546 as an inverter with an input voltage clamp. Bootstrapping the clamp diodes at the inverting input minimizes the voltage across the clamps and keeps the leakage due to the diodes low. Low leakage diodes (less Figure 38. Sample and Difference Circuit for Measuring Electrometer Leakage Currents MEASURING ELECTROMETER LEAKAGE CURRENTS Figure 36. Follower with Input Current Limit There are a number of methods used to test electrometer leakage currents, including current integration and direct current to voltage conversion. Regardless of the method used, board and interconnect cleanliness, proper choice of insulating materials (such as Teflon or Kel-F), correct guarding and shielding techniques and care in physical layout are essential for making accurate leakage measurements. Figure 38 is a schematic of the sample and difference circuit which is useful for measuring the leakage currents of the AD546 and other electrometer amplifiers. The circuit uses two AD549 electrometer amplifiers (A and B) as current to voltage converters with high value (1010 ) sense resistors (RSa and RSb). R1 and R2 provide for an overall circuit sensitivity of 10 fA/mV (10 pA full scale). CC and CF provide noise suppression and loop compensation. CC should be a low leakage polystyrene capacitor. An ultralow-leakage Kel-F test socket is used for con-10- REV. A Figure 37. Input Voltage Clamp with Diodes AD546 tacting the device under test. Rigid Teflon coaxial cable is used to make connections to all high impedance nodes. The use of rigid coax affords immunity to error induced by mechanical vibration and provides an outer conductor for shielding. The entire circuit is enclosed in a grounded metal box. The test apparatus is calibrated without a device under test present. A five minute stabilization period after the power is turned on is required. First, VERR1 and VERR2 are measured. These voltages are the errors caused by offset voltages and leakage currents of the current to voltage converters. VERR1 = 10 (VOSA - IBA x RSa) VERR2 = 10 (VOSB - IBB x RSb) Once measured, these errors are subtracted from the readings taken with a device under test present. Amplifier B closes the feedback loop to the device under test, in addition to providing current to voltage conversion. The offset error of the device under test appears as a common-mode signal and does not affect the test measurement. As a result, only the leakage current of the device under test is measured. VA - VERR1 = 10[RSa x IB(+)] VX - VERR2 = 10[RSb x IB(-)] Although a series of devices can be tested after only one calibration measurement, calibration should be updated periodically to compensate for any thermal drift of the current-to-voltage converters or changes in the ambient environment. Laboratory results have shown that repeatable measurements within 10 fA can be realized when this apparatus is properly implemented. These results are achieved in part by the design of the circuit, which eliminates relays and other parasitic leakage paths in the high impedance signal lines, and in part by the inherent cancellation of errors through the calibration and measurement procedure. PHOTODIODE INTERFACE Input current, IB, will contribute an output voltage error, VE1, proportional to the feedback resistance: VE1 = IB x RF The op amp's input voltage offset will cause an error current through the photodiode's shunt resistance, RS: I = VOS/RS The error current will result in an error voltage (VE2) at the amplifier's output equal to: VE2 = (1 +RF/RS) VOS Given typical values of photodiode shunt resistance (on the order of 109 ), RF/RS can be greater than one, especially if a large feedback resistance is used. Also, RF/RS will increase with temperature, as photodiode shunt resistance typically drops by a factor of two for every 10C rise in temperature. An op amp with low offset voltage and low drift helps maintain accuracy. Figure 40. Photodiode Preamp DC Error Sources Photodiode Preamp Noise The AD546's 1 pA current and low input offset voltage make it a good choice for very sensitive photodiode preamps (Figure 39). The photodiode develops a signal current, IS, equal to: IS = R x P where P is light power incident on the diode's surface in watts and R is the photodiode responsivity in amps/watt. RF converts the signal current to an output voltage: VOUT = RF x IS Noise limits the signal resolution obtainable with the preamp. The output voltage noise divided by the feedback resistance is the minimum current signal that can be detected. This minimum detectable current divided by the responsivity of the photodiode represents the lowest light power that can be detected by the preamp. Noise sources associated with the photodiode, amplifier, and feedback resistance are shown in Figure 41; Figure 42 is the voltage spectral density versus frequency plot of each of the noise source's contribution to the output voltage noise (circuit parameters in Figure 40 are assumed). Each noise source's rms contribution to the total output voltage noise is obtained by integrating the square of its spectral density function over frequency. The rms value of the output voltage noise is the square root of the sum of all contributions. Minimizing the total area under these curves will optimize the preamplifier's resolution for a given bandwidth. Figure 39. Photodiode Preamp DC error sources and an equivalent circuit for a small area (0.2 mm square) photodiode are indicated in Figure 40. Figure 41. Photodiode Preamp Noise Sources REV. A -11- AD546 Figure 42. Photodiode Preamp Noise Sources' Spectral Density vs. Frequency The photodiode preamp in Figure 39 can detect a signal current of 26 fA rms at a bandwidth of 16 Hz, which assuming a photodiode responsivity of 0.5 A/W, translates to a 52 fW rms minimum detectable power. The photodiode used has a high source resistance and low junction capacitance. CF sets the signal bandwidth with RF and also limits the "peak" in the noise gain that multiplies the op amp's input voltage noise contribution. A single pole filter at the amplifier's output limits the op amp's output voltage noise bandwidth to 26 Hz, a frequency comparable to the signal bandwidth. This greatly improves the preamplifier's signal to noise ratio (in this case, by a factor of three). Photodiode Array Processor Figure 43. Photodiode Array Processor The AD546 is a cost effective preamp for multichannel applications, such as amplifying signals from photo diode arrays, as illustrated in Figure 43. An AD546 preamp converts each of the diodes' output currents to a voltage. An 8 to 1 multiplexer switches a particular preamp output to the input of an AD1380 16-bit sampling ADC. The output of the ADC can be displayed or put onto a databus. Additional preamps and muxes can be added to handle larger arrays. Layout of multichannel circuits is critical. Refer to "PC board notes" for guidance. pH PROBE AMPLIFIER Figure 44. pH Probe Amplifier OUTLINE DIMENSIONS Dimensions shown in inches and (mm). The circuit in Figure 44 illustrates the use of the AD546 as a pH probe amplifier. As with other electrometer applications, the use of guarding, shielding, Teflon standoffs, etc., is a must in order to capitalize on the AD546's low input current. If an AD546J (1 pA max input current) is used, the error contributed by input current will be held below 10 mV for pH electrode source impedances up to 109 . Input offset voltage (which can be trimmed) will be below 2 mV. Refer to AD549 data sheet for temperature compensated pH probe amplifier circuit. -12- REV. A PRINTED IN U.S.A. A pH probe can be modeled as a mV-level voltage source with a series source resistance dependent upon the electrode's composition and configuration. The glass bulb resistance of a typical pH electrode pair falls between 106 and 109 . It is, therefore, important to select an amplifier with low enough input currents such that the voltage drop produced by the amplifier's input bias current and the electrode resistance does not become an appreciable percentage of a pH unit. Mini-DIP (N) Package C1291-10-7/89 |
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